Comp 150-001, TTh, 11:00-2:00, DH-339
Class 6
Midterm is Tuesday, June 9
S-R latch: beginnings of memory
Note that, due to the feedback, this is not a combinatorial circuit.
Most people make SR latches
out of a pair of NOR gates. Our book uses NAND gates. The result is
that the gate works "backwards": 1 represents quiet, and 0 represents do something. The forbidden state in our book is (0,0). You set S or R (but not both!) to 0 to update the latch state.
However, the applet
version switches back to using a pair of NOR gates. Thus, the applet
version normal state is (0,0); the set state is (1,0), and the reset
state is (0,1). Then the applet works.
The books' version is typically denoted SR-with-a-bar-overhead, or inverted-SR latches. Inverted latches are easier to build, because NAND gates are slightly cheaper (in terms of component count) than NOR gates.
S=R=1: saved-data state
S=0,R=1: SET state: set to 0
R=0,S=1: RESET state
S-R latches are used for registers and other static RAM applications.
Gated SR latch: add some gates in front (two AND gates in parallel,
with their outermost inputs being S and R, and the pair of innermost
inputs being the Enable line), so that if Enable is set (1) then S or R
can write, but if Enable is 0 then nothing happens.
Flip-flop: the Enable line is clocked, 0-1-0-1-0-1-0-1-...
SR flipflop: straightforward gated SR latch
D-flipflop: R = not S. The S input is renamed D. If D=0 when enabled, we write 0; if D=1, we write 1.
Dynamic ram: each bit is stored in a tiny capacitor, with a transistor
for refresh. The whole DRAM unit is "strobed" peridoically (every few
milliseconds) to refresh it.
To read a bit: everything is in a square array, say 32 x 32. There are
32 horizontal wires, 32 vertical wires, and 1024 bits in all, one bit
at each intersection of a pair of wires. To read a bit, you turn on
those two wires.
PEP/7
7.3: machine language, opcodes, 12-bit addressing, PC, IR, A, N, Z
instruction format: 5 opcode bits, 1 zero bit, 2 mode bits
immediate v direct modes
some instructions and operands:
supersimple: no MUL, and hence no nontrivial expression evaluation. Everything is addition or subtraction, which can be evaluated left-to-right
PIP
opcode format, operand
opcodes
immediate v direct (assembler notation more natural?)
data addresses (names): implicit!
code addresses (labels)
weirdness in comparisons and testing; no easy way to branch to FOO if the Accumulator is < 0.
bit operations: AND, OR, COMPLEMENT, XOR, SHIFT. We don't use them, but some folks do. Heavily.
examples from directory
- simple.asm: code to store 4+3 into N.
- arith.asm: code to evaluate the expression Z = (W+X)*Y/2
- ifElse.asm, ifElse2.asm: code to execute a couple if-else statements
- sum2n.asm: finds n+(n-1)+...+3+2+1
- gcd.asm
- exp.asm
What about arrays? How would we access A[i]?
calculate offset in ACC
access memory location A+ACC? There is no way in PIP (or in PEP/7 using the addressing modes provided) to access memory at a computed location.
Pointers: addresses stored in data
What if there's recursion, or even if there's not? The stack concept.
What about labels? Do addresses have to be absolute? Relative addressing, usually given as an offset from a base register (sometimes the PC itself, which works well for code addresses).
What about subroutines? How do we call one function from another? If
function f(x) can be called from any of several places, where do we
return to? Stored return address!
Is the Stack Pointer a user convention, or is it part of the hardware? Interrupts: sort of like "asynchronous" function calls made from the external hardware.
Segmented addressing: 16-bit addressing, but always including a 32 (or
24 or 20) bit base register. Thus, we can refer to one 64KB address
space at a time (per base register), but we can change the base
register to change our view of memory. (Intel was big on this until the
386; it was and is a kludge, though there are arguments on its behalf.)
Flat memory model