Comp 150-001, TTh, 11:00-2:00, DH-339

Class 5

Midterm is Tuesday, June 9

S-R latch: beginnings of memory

Note that, due to the feedback, this is not a combinatorial circuit.

Most people make SR latches out of a pair of NOR gates. Our book uses NAND gates. The result is that the gate works "backwards": 1 represents quiet, and 0 represents do something. The forbidden state in our book is (0,0). You set S or R (but not both!) to 0 to update the latch state.

The books' version is typically denoted SR-with-a-bar-overhead, or inverted-SR latches. Inverted latches are easier to build, because NAND gates are slightly cheaper (in terms of component count) than NOR gates.

S=R=1: saved-data state

S=0,R=1: SET state: set to 0

R=0,S=1: RESET state

S-R latches are used for registers and other static RAM applications.

Gated SR latch: add some gates in front (two AND gates in parallel, with their outermost inputs being S and R, and the pair of innermost inputs being the Enable line), so that if Enable is set (1) then S or R can write, but if Enable is 0 then nothing happens.

Flip-flop: the Enable line is clocked, 0-1-0-1-0-1-0-1-...
SR flipflop: straightforward gated SR latch
D-flipflop: R = not S. The S input is renamed D. If D=0 when enabled, we write 0; if D=1, we write 1.

Dynamic ram: each bit is stored in a tiny capacitor, with a transistor for refresh. The whole DRAM unit is "strobed" peridoically (every few milliseconds) to refresh it.

To read a bit: everything is in a square array, say 32 x 32. There are 32 horizontal wires, 32 vertical wires, and 1024 bits in all, one bit at each intersection of a pair of wires. To read a bit, you turn on those two wires.

clocking:
how do we get to a machine that does things in sequence?
The clock signal tells the machine to go to the next step; the clock pulses are spaced far enough apart that each step "settles down" (ie completes) in one clock pulse.

Some steps in the development of synchronous operation:

    Counter:            
    Each time clock input goes from 0 to 1, output binary number increments by 1
    (0001 is added to output value)

Basic counter:
Low-order bit is toggled 0,1,0,1 by the clock (actually, half the clock speed)
Every other bit looks at its predecessor bit. If the predecessor bit goes from 1 to 0, they must change: from 1 to 0 or 0 to 1. 0->1 is just incrementing; 1->0 means that the subsequent bit will also change.

    Attach a counter to a selector:
    Each time input goes from 0 to 1, a new output line is activated:
                  +--------------
    --------------+--------------
                  +--------------
                  +--------------

Basic model:
on each clock 0->1 transition, computer does ONE STEP.
Settles down afterward, & waits for next transition

Microcode steps:

ALU: do all operations, have a demultiplexor select which one, based on the opcode


PEP/7

7.3: machine language, opcodes, 12-bit addressing, PC, IR, A, N, Z
instruction format: 5 opcode bits, 1 zero bit, 2 mode bits
immediate v direct modes

some instructions and operands:

7.5:
Assembler mnemonics (p 212)
pseudo-operations (data, or .bss)
Programs:
    1. Hello
    2. read-and-add
    3. read a list of numbers



Python

Graphics basics